1. Field of the Invention
Embodiments of the invention relate to semiconductor systems containing power devices for being used for systems such as electric power inverters.
2. Related Art
Electric power inverters are widely used for systems such as a PCS (Power Conditioning Subsystem) and a UPS (Uninterruptible Power Supply) each provided with a function of converting electric power generated by an electric power generation unit such as a solar cell, a fuel cell or a gasoline engine to system electric power.
In such an electric power inverter, a semiconductor module is used in which power devices such as IGBTs (Insulated Gate Bipolar Transistors) and FWDs (Free Wheeling Diodes) are surface mounted on an insulating substrate to be contained in a resin case.
As an example of a semiconductor module used for an electric power inverter of such kind, the power semiconductor module proposed in Japanese Patent Application Publication No. JP-A-2012-110095 (referred to herein as “JP-A-2012-110095”) is proposed, for example.
The power semiconductor module contains in a case a circuit of a three-level inverter in one phase. In the three-level inverter circuit, a U terminal and M terminal, in each of which a current flows in the direction opposite to the direction of the other, are wired so that they are arranged with one being laid over the other in close proximity thereto to thereby reduce inductance in the case.
Moreover, as another example of a related module, the power semiconductor module described in Japanese Patent Application Publication No. JP-A-2011-254672 (referred to herein as “JP-A-2011-254672”) is proposed. In the power semiconductor module, when forming a three-level inverter like the three-level inverter described in JP-A-2012-110095, the external terminals of P, M, N and U thereof are arranged in a straight line with the M terminal made to be formed of two terminals M1 and M2 so as to be in the order of M1, P, N, M2 and U or in the order of M1, N, P, M2 and U. The configuration prevents a jumping up voltage from becoming large which is produced by the influence of wiring inductance when the operation mode is changed from the three-level mode to the two-level mode.
Further, as further another example of a related module, the semiconductor module described in Japanese Patent Application Publication No. JP-A-2008-193779 (referred to herein as “JP-A-2008-193779”) is proposed. The semiconductor module, by containing in one package a series connection circuit of IGBTs, connected between the P terminal and the N terminal of the DC power supply, and an AC switching device, connected between the connection point of the series connection circuit and the neutral point of the DC power supply, is provided so as to actualize reduction in wiring inductance and reduction in the price of the system. Here, as the cases of forming a three-level inverter, there are described the case of providing a bidirectional switch by connecting two IGBTs in series each with a diode connected in inverse parallel thereto and the case of providing a bidirectional switch by connecting two reverse blocking IGBTs in inverse parallel. The reverse blocking IGBT is an IGBT having a reverse voltage withstand characteristic.
In addition, as still another example of a related module, the semiconductor system described in Japanese Patent Application Publication No. JP-A-2011-193646 (referred to herein as “JP-A-2011-193646”) is proposed. The semiconductor system is provided with a series connection circuit of IGBTs, which is connected between the P terminal and the N terminal of the DC power supply of a three-level inverter circuit, and an intermediate terminal provided at the connection point of a first and second IGBTs, which are connected in series between the connection point of the series connection circuit and the neutral point of the DC power supply each having a diode connected in inverse parallel thereto. By the configuration, an insulation test can be carried out while preventing breakage of the IGBTs and diodes in the semiconductor system.
Furthermore, as still further another example of a related module, the semiconductor system described in Japanese Patent Application Publication No. JP-A-2002-368192 (referred to herein as “JP-A-2002-368192”) is proposed. The semiconductor system is a large capacity semiconductor system used for a system such as an inverter in which three IGBT chips are provided on an insulating substrate so as to be arranged in a zigzag pattern so as to be connected in parallel to one another.
Incidentally, with respect to each of the examples of the related semiconductor modules described in JP-A-2012-110095, JP-A-2011-254672 and JP-A-2008-193779, although there is a disclosure of reducing the inductance therein, no consideration is found with respect to the heat generation in the semiconductor system.
Moreover, with respect to the example of the related semiconductor system described in JP-A-2011-193646, there is only a disclosure of the configuration of the three-level inverter circuit and no consideration is found with respect to the heat generation in the semiconductor system.
In JP-A-2002-368192, however, it is described that by arranging the semiconductor chips in a zigzag pattern, the heat generated in the semiconductor chips is efficiently dispersed to reduce interference by heat. In the example of the related semiconductor system described in JP-A-2002-368192, however, although generated heat can be dispersed to be uniformly distributed by arranging the semiconductor chips in a zigzag pattern, the heat is to be generated on the whole surface of the semiconductor system. This causes an unsolved problem of enabling no generated heat to be effectively dispersed.